How Long to Read Digital Timing Macromodeling for VLSI Design Verification

How Long Does it Take to Read Digital Timing Macromodeling for VLSI Design Verification?

It takes the average reader 4 hours and 30 minutes to read Digital Timing Macromodeling for VLSI Design Verification by Jeong-Taek Kong

Assuming a reading speed of 250 words per minute. Learn more

Description

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

How long is Digital Timing Macromodeling for VLSI Design Verification?

Digital Timing Macromodeling for VLSI Design Verification by Jeong-Taek Kong is 265 pages long, and a total of 67,575 words.

This makes it 89% the length of the average book. It also has 83% more words than the average book.

How Long Does it Take to Read Digital Timing Macromodeling for VLSI Design Verification Aloud?

The average oral reading speed is 183 words per minute. This means it takes 6 hours and 9 minutes to read Digital Timing Macromodeling for VLSI Design Verification aloud.

What Reading Level is Digital Timing Macromodeling for VLSI Design Verification?

Digital Timing Macromodeling for VLSI Design Verification is suitable for students ages 12 and up.

Note that there may be other factors that effect this rating besides length that are not factored in on this page. This may include things like complex language or sensitive topics not suitable for students of certain ages.

When deciding what to show young students always use your best judgement and consult a professional.

Where Can I Buy Digital Timing Macromodeling for VLSI Design Verification?

Digital Timing Macromodeling for VLSI Design Verification by Jeong-Taek Kong is sold by several retailers and bookshops. However, Read Time works with Amazon to provide an easier way to purchase books.

To buy Digital Timing Macromodeling for VLSI Design Verification by Jeong-Taek Kong on Amazon click the button below.