It takes the average reader 3 hours and 37 minutes to read Minimizing and Exploiting Leakage in VLSI Design by Nikhil Jayakumar
Assuming a reading speed of 250 words per minute. Learn more
Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.
Minimizing and Exploiting Leakage in VLSI Design by Nikhil Jayakumar is 214 pages long, and a total of 54,356 words.
This makes it 72% the length of the average book. It also has 66% more words than the average book.
The average oral reading speed is 183 words per minute. This means it takes 4 hours and 57 minutes to read Minimizing and Exploiting Leakage in VLSI Design aloud.
Minimizing and Exploiting Leakage in VLSI Design is suitable for students ages 12 and up.
Note that there may be other factors that effect this rating besides length that are not factored in on this page. This may include things like complex language or sensitive topics not suitable for students of certain ages.
When deciding what to show young students always use your best judgement and consult a professional.
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