It takes the average reader 3 hours and 30 minutes to read Simulated Annealing for VLSI Design by D.F. Wong
Assuming a reading speed of 250 words per minute. Learn more
This monograph represents a summary of our work in the last two years in applying the method of simulated annealing to the solution of problems that arise in the physical design of VLSI circuits. Our study is experimental in nature, in that we are con cerned with issues such as solution representations, neighborhood structures, cost functions, approximation schemes, and so on, in order to obtain good design results in a reasonable amount of com putation time. We hope that our experiences with the techniques we employed, some of which indeed bear certain similarities for different problems, could be useful as hints and guides for other researchers in applying the method to the solution of other prob lems. Work reported in this monograph was partially supported by the National Science Foundation under grant MIP 87-03273, by the Semiconductor Research Corporation under contract 87-DP- 109, by a grant from the General Electric Company, and by a grant from the Sandia Laboratories.
Simulated Annealing for VLSI Design by D.F. Wong is 206 pages long, and a total of 52,736 words.
This makes it 70% the length of the average book. It also has 64% more words than the average book.
The average oral reading speed is 183 words per minute. This means it takes 4 hours and 48 minutes to read Simulated Annealing for VLSI Design aloud.
Simulated Annealing for VLSI Design is suitable for students ages 12 and up.
Note that there may be other factors that effect this rating besides length that are not factored in on this page. This may include things like complex language or sensitive topics not suitable for students of certain ages.
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